32k channel readout IC for single photon counting pixel detectors with 75$\mu$m pitch, dead time of 85 ns, 9 ${e^{-}rms}$ offset spread and 2\% rms gain spread
PBN-AR
Instytucja
Wydział Elektrotechniki, Automatyki, Informatyki i Inżynierii Biomedycznej (Akademia Górniczo-Hutnicza im. Stanisława Staszica w Krakowie)
Informacje podstawowe
Główny język publikacji
EN
Czasopismo
IEEE Transactions on Nuclear Science
ISSN
0018-9499
EISSN
1558-1578
Wydawca
Institute of Electrical and Electronics Engineers
Rok publikacji
2016
Numer zeszytu
2
Strony od-do
1155--1161
Numer tomu
63
Link do pełnego tekstu
Identyfikator DOI
Liczba arkuszy
0.5
Słowa kluczowe
EN
pixel detectors
X-ray imaging
single photon counting
matching
Streszczenia
Język
EN
Treść
This paper presents a readout integrated circuit called UFXC32k, designed for hybrid pixel semiconductor detectors used in X-ray imaging applications. The UFXC32k integrated circuit, designed in a CMOS 130 nm process, contains about 50 million transistors in the area of $9.64;hbox{mm} times 20.15;hbox{mm}$. The core of the IC is a matrix of $128 times 256$ square-shaped pixels of ${hbox{75}};muhbox{m}$ pitch. Each pixel contains a charge sensitive amplifier, a shaper, two discriminators, and two 14-bit ripple counters. The analog front-end electronics allow processing of sensor signals of both polarities (holes and electrons). The UFXC32k chip is bump-bonded to a pixel silicon sensor and is fully characterized using X-ray radiation. The measured equivalent noise charge for the standard settings is equal to $123 {{rm e}^ - };hbox{rms}$ (for the peaking time of 40 ns) and each pixel dissipates $26;muhbox{W}$. Thanks to the use of trim blocks working in each pixel independently, an effective offset spread calculated to the input is only $9 {{rm e}^ - };hbox{rms}$ with a gain spread of 2%. The maximum count rate per pixel depends mainly on effective CSA feedback resistance. Dead time in the front end can be set as low as 85 ns. In the continuous readout mode, a user can select the number of bits read out from each pixel to optimize the UFXC32k frame rate, e.g., for a readout of 2 bits/pixel with 200 MHz clock, the frame rate is equal to 23 kHz.
Cechy publikacji
original article
peer-reviewed
Inne
System-identifier
idp:097437
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