An Ultra-Low-Energy Analog Comparator for A/D Converters in CMOS Image Sensors
PBN-AR
Instytucja
Wydział Elektroniki, Telekomunikacji i Informatyki (Politechnika Gdańska)
Informacje podstawowe
Główny język publikacji
en
Czasopismo
CIRCUITS SYSTEMS AND SIGNAL PROCESSING (25pkt w roku publikacji)
ISSN
0278-081X
EISSN
Wydawca
DOI
URL
Rok publikacji
2017
Numer zeszytu
12
Strony od-do
4829-4843
Numer tomu
36
Identyfikator DOI
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Autorzy
(liczba autorów: 1)
Słowa kluczowe
ANALOG COMPARATOR
CMOS
CMOS IMAGE SENSOR
SLOPE ANALOG-TO-DIGITAL CONVERTER
VOLTAGE-TO-TIME CONVERTER
Streszczenia
Język
Treść
This paper proposes a new solution of an ultra-low-energy analog comparator, dedicated to slope analog-to-digital converters (ADC), particularly suited for CMOS image sensors (CISs) featuring a large number of ADCs. For massively parallel imaging arrays, this number may be as high as tens-hundreds of thousands ADCs. As each ADC includes an analog comparator, the number of these comparators in CIS is always high. Detailed analysis shows that power dissipation of a comparator contributes significantly to a total power consumption of an ADC. Thus, minimization of the comparator energy consumption during the analog-to-digital (A/D) conversion of an image frame is crucial for design of CMOS image sensors. Compared to classical dynamic or continuous-time comparators operating in the slope ADC, under the same bias conditions, the proposed comparator shows a 2–3 orders of magnitude reduction of the power consumption. In addition, the proposed topology shows a simple and compact layout and does not require a power-down mechanism. The circuit has been simulated in detail for a 0.18-μm CMOS technology under two different power supply voltages of 1.8 and 1 V. While implemented in a 12-bit slope ADC of a massively parallel CIS, operating at a speed 1000 fps, the energy required for A/D conversion is 0.5 pJ.
Inne
System-identifier
144292
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