An FPGA Based High Speed Error Resilient Data Aggregation and Control for High Energy Physics Experiment
PBN-AR
Instytucja
Wydział Elektroniki i Technik Informacyjnych (Politechnika Warszawska)
Informacje podstawowe
Główny język publikacji
en
Czasopismo
IEEE Transactions on Nuclear Science (35pkt w roku publikacji)
ISSN
0018-9499
EISSN
Wydawca
IEEE Nuclear and Plasma Sciences Society
DOI
Rok publikacji
2017
Numer zeszytu
3
Strony od-do
933-944
Numer tomu
64
Identyfikator DOI
Liczba arkuszy
0.55
Autorzy
(liczba autorów: 6)
Pozostali autorzy
+ 5
Słowa kluczowe
en
field programmable gate arrays
high energy physics instrumentation computing
DAQ
FPGA-based high-speed error resilient data aggregation
HEP experiment
back-end data processing computing nodes
back-end processing nodes
data acquisition system
data corruption
field-programmable gate array
high energy physics experiment
memory management algorithm
Adaptive optics
Data acquisition
Decoding
Delays
Detectors
Field programmable gate arrays
High-speed optical techniques
Cyclic redundancy checking (CRC)
data acquisition
error correction
field-programmable array (FPGA)
high energy physics (HEP)
orthogonal concatenated code
Streszczenia
Język
en
Treść
Due to the dramatic increase of data volume in modern High Energy Physics (HEP) experiments, a robust highspeed data acquisition system (DAQ) is very much needed to gather the data generated during different nuclear interactions. As the DAQ works under harsh radiation environment, there is a fair chance of data corruption due to various energetic particles like alpha, beta or neutron. Hence, a major challenge in the development of DAQ in HEP experiment is to establish an error resilient communication system between front-end sensors or detectors and back-end data processing computing nodes. Here we have implemented the DAQ using Field Programmable Gate Array (FPGA) due to some of its inherent advantages over the Application Specific Integrated Circuits (ASIC). A novel orthogonal concatenated code and cyclic redundancy checking (CRC) have been used to mitigate the effects of data corruption in the user data. Scrubbing with 32bit CRC has been used against error in the configuration memory of FPGA. Data from frontend sensors will reach to the back-end processing nodes through multiple stages that may add an uncertain amount of delay to the different data packets. We have also proposed a novel memory management algorithm that helps to process the data at the back-end computing nodes removing the added path delays. To the best of our knowledge, the proposed FPGA-based DAQ utilizing optical link with channel coding and efficient memory management modules can be considered as first of its kind. Performance estimation of the implemented DAQ system is done based on resource utilization, bit error rate (BER), efficiency and robustness against radiation.
Inne
System-identifier
WUTa6a39460d29c4735918da8d7c5da6112
CrossrefMetadata from Crossref logo
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