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  • 12.10.2015 12:21:44
  • Grzegorz Łabiak [1]
  • Marian Adamski [1]
  • Michał Doligalski [1]
  • Jacek Tkacz [1]
  • Arkadiusz Bukowiec [1]
  • [1] Institute of Computer Engineering and Electronics, University of Zielona Góra, Licealna 9, 65-417 Zielona Góra, Poland
  • Brak afiliacji
  1. Michał Doligalski, Marian Adamski, Hierarchical Configurable Petri Net Modeling in VHDL. International Journal of Electronics and Telecommunications 2012; 58, 4, 397-402
  2. Michał Doligalski, Arkadiusz Bukowiec, Partial Reconfiguration in the Field of Logic Controllers Design. International Journal of Electronics and Telecommunications 2013; 59, 4, 351-356
  3. Arkadiusz Bukowiec, Marian Adamski, Synthesis of Macro Petri Nets into FPGA with Distributed Memories. International Journal of Electronics and Telecommunications 2012; 58, 4, 403-410
  4. Jacek Tkacz, Marian Adamski, Structured Mapping of Petri Net States and Events for FPGA Implementations. International Journal of Electronics and Telecommunications 2013; 59, 4, 331-339
  5. Arkadiusz Bukowiec, Jacek Tkacz, Tomasz Gratkowski, Tomasz Gidlewicz, Implementation of Algorithm of Petri Nets Distributed Synthesis into FPGA. International Journal of Electronics and Telecommunications 2013; 59, 4, 317-324
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  3. M. Doligalski and M. Węgrzyn, "Partial reconfiguration-oriented design of logic controllers," Proceedings of SPIE : Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2007, vol. Vol. 6937, p. [10], 2007.
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  8. M. Doligalski and M. Adamski, "Exceptions and deep history state handling using dual specification," Electrical Review, no. No. 9, pp. 123-125, 2010.
  9. G. čabiak and M. Adamski, "Concurrent processes synchronisation in statecharts for FPGA implementation," in Proceedings of IEEE East-West Design & Test Symposium EWDTS'08, Kharkov National University of Radioelectronics. Lviv, Ukraine: Lviv, The Institute of Electrical and Electronics Engineers, Inc., 2008, pp. 59-64.
  10. K. Biliński, M. Adamski, J. Saul, and E. Dagless, "Petri-net-based algorithms for parallel-controller synthesis," IEE Proceedings - Computers and Digital Techniques, vol. Vol. 141, no. No. 6, pp. 405-412, 1994.
  11. A. Karatkevich, Dynamic Analysis of Petri Net-Based Discrete Systems, ser. Lecture Notes in Control and Information Sciences. Berlin: Springer-Verlag, 2007, vol. 356.
  12. A. Bukowiec and L. Gomes, "Partitioning of Mealy finite state machines," in Preprints of the 4th IFAC Workshop Discrete-Event System Design DESDes'09, Gandia Beach, Spain, 2009, pp. 21-26.
  13. A. Wegrzyn, "Parallel algorithm for computation of deadlocks and traps in Petri nets," in 10th IEEE International Conference Emering Technologies and Factory Automation ETFA'05, vol. 1, Universita di Catania. Catania, Italy: Piscataway, IEEE Operation Center, 2005, pp. 143-148.
  14. J. H. Gallier, Logic for Computer Science: Foundations of Automatic Theorem Proving. New York: Harper & Row Publishers, 1985. [Online]. Available: http://www.cis.upenn.edu/jean/gbooks/logic.html http://www.cis.upenn.edu/jean/gbooks/logic.html
  15. J. Tkacz, "State machine type colouring of Petri net by means of using a symbolic deduction method," Measurement Automation and Monitoring, vol. Vol. 53, no. No. 5, pp. 120-122, 2007.
  16. M. Adamski, "Petri nets in ASIC design," Applied Mathematics and Computer Science, vol. Vol. 3, no. No. 1, pp. 169-179, 1993.
  17. M. Zwoliński, Digital System Design with VHDL, 2nd ed. New Jersy: Prentice Hall, 2004.
  18. M. Puczyńska, G. Łabiak, and P. Wolański, "Programowa implementacja konwersji sieci petriego na jezyk VHDL," in Materiały III Krajowej Konferencji Naukowej Reprogramowalne Układy Cyfrowe RUC 2000, Szczecin, Poland, 2000, pp. 285-291.
  • J. Tkacz, "State machine type colouring of Petri net by means of using a symbolic deduction method," Measurement Automation and Monitoring, vol. Vol. 53, no. No. 5, pp. 120-122, 2007. - Pomiary Automatyka Kontrola
  • G. Łabiak and G. Borowik, "Statechart-based controllers synthesis in fpga structures with embedded array blocks," International Journal of Electronics and Telecommunications, vol. Vol. 56, no. no 1, pp. 13-24, 2010. - International Journal of Electronics and Telecommunications
  • M. Adamski, "Petri nets in ASIC design," Applied Mathematics and Computer Science, vol. Vol. 3, no. No. 1, pp. 169-179, 1993. - INT J AP MAT COM-POL