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  • 12.10.2015 12:23:25
  • Adam Milik [1]
  • Edward Hrynkiewicz [1]
  • [1] Institute of Electronics, Silesian University of Technology, Gliwice, Poland
  • Brak afiliacji
Nie znaleziono publikacji cytujących ten artykuł
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  23. Xilinx, UG073, XtremeDSP for Virtex-4 FPGAs User Guide. Xilinx, 2007.
  24. Xilinx, UG389, Spartan-6 FPGA DSP48A1 Slice. Xilinx, 2009.
  25. Xilinx, DS302, Virtex-4 FPGA Data Sheet: DC and Switching Characteristics. Xilinx, 2007.
  26. Xilinx, DS162 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics. Xilinx, 2011.
  27. G. Hachtel and F. Somenzi, Logic synthesis and verification algorithms. Springer, 1996.
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  29. A. Mishchenko, S. Cho, S. Chatterjee, and R. Brayton, "Combinational and sequential mapping with priority cuts," in Precedeenigs of Computer Aided Design Conference. IEEE, 2007, pp. 354-361.
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  • J. Welch, "Translating unrestricted relay ladder logic into boolean form." Computers in Industry, vol. 20, pp. 45-61, 1992. - COMPUT IND
  • S. Akers, "Binary decision diagrams," IEEE Transactions on Computers, vol. C-27, pp. 509-516, June 1978. - IEEE T COMPUT
  • R. E. Bryant, "Graph based algorithms for boolean function manipulation," IEEE Transactions on Computers, vol. C-35, pp. 677-691, August 1986. - IEEE T COMPUT